1. Field of the Invention
The present invention relates to a semiconductor memory device and a semiconductor module including a plurality of such semiconductor memory devices, and particularly relates to the semiconductor memory device, which can enter a test mode in the module, as well as the semiconductor module.
2. Description of the Background Art
In recent years, attention has been given to a DIMM (Double Inline Memory Module), which operates in synchronization with a clock signal having a frequency of 50 MHz or more. The DIMM has two semiconductor modules formed on the opposite sides of one substrate, respectively. The semiconductor module includes a plurality of DRAMs (Dynamic Random Access Memories).
In particular, the semiconductor module used in a registered DIMM (RDIMM) includes a plurality of DRAMs, and is configured to perform input/output of data to and from the DRAMs in synchronization with a clock signal having a high frequency of 50 MHz or more.
Referring to FIG. 33, a semiconductor module 620 used in an RDIMM includes DRAMs 631-639, registered buffers 650 and 660, and a PLL circuit 670. Semiconductor module 630 used in the RDIMM includes DRAMs 640-648.
PLL circuit 670 generates a clock signal having a high frequency of 50 MHz or more and adjusts timing, according to which input signals are applied to DRAMs 631-648.
Referring to FIG. 34, each of registered buffer circuits 650 and 660 receives the control signal, and address signal, which are externally applied, and coverts the voltage levels forming the control signals to the voltage levels to be used in corresponding semiconductor module 620 or 630 for applying them to DRAMs 631-648. Registered buffer 650 applies the input signal to DRAMs 631-639 of semiconductor module 620, and registered buffer 660 applies the input signal to DRAMs 640-648 of semiconductor module 630.
Each of DRAMs 631-648 includes a test mode circuit 700 shown in FIG. 35. Referring to FIG. 35, test mode circuit 700 includes P-channel MOS transistors 701 and 703, N-channel MOS transistors 702, 704 and 705, an inverter 711 and an AND gate 712.
P- and N-channel MOS transistors 701 and 702 are connected in series between a power supply node 706 and a node 710. P- and N-channel MOS transistors 703 and 704 are connected in series between power supply node 706 and node 710. P- and N-channel MOS transistors 703 and 704 are connected in parallel to P- and N-channel MOS transistors 701 and 702.
P-channel MOS transistors 701 and 703 receive a voltage on power supply node 706 as a substrate voltage. A voltage on a node 708 is supplied to gate terminals of P-channel MOS transistors 701 and 703. N-channel MOS transistor 702 receives a signal SVIH on its gate terminal, and N-channel MOS transistor 704 receives a reference voltage VDD on its gate terminal. Signal SVIH is formed of a high potential, which is input via a control pin such as an address pin in a test mode. N-channel MOS transistor 705 is connected between node 710 and a ground node 707, and receives a control signal CSC on its gate terminal.
A differential circuit formed of P-channel MOS transistors 701 and 703 as well as N-channel MOS transistors 702, 704 and 75 is a differential comparing circuit of a current mirror type, which becomes active in response to control signal CSC of H (logical high) level, and compares the voltage level of signal SVIH with the voltage level of reference voltage VDD for outputting a result of the comparison from a node 709. When the voltage level of signal SVIH is higher than the voltage level of reference voltage VDD, the voltage on node 709 is lower than the voltage on node 708, and the differential circuit outputs a signal of L (logical low) level to inverter 711. When the voltage level of signal SVIH is lower than the voltage level of reference voltage VDD, the voltage on node 709 is higher than the voltage on node 708 so that a signal of H level is output to inverter 711.
Inverter 711 inverts the logical level of the signal sent from node 709, and sends it to AND gate 712. AND gate 712 performs a logical AND on output signal of inverter 711 and control signals CSA and CSB.
For shifting DRAMs 631-648 to the test mode, test mode circuit 700 receives control signals CSA, CSB and CSC of H level, and also receives signal SVIH formed of a voltage level higher than the voltage level in a normal operating range. Thereby, N-channel MOS transistor 705 is turned on, and the differential circuit formed of P-channel MOS transistors 701 and 703 as well as N-channel MOS transistors 702 and 704 compares the voltage level of signal SVIH with the voltage level of reference voltage VDD, and sends the signal of L level from node 709 to inverter 711. Inverter 711 inverts this signal of L level, and outputs the signal of H level to AND gate 712. AND gate 712 performs a logical AND on the signal of H level sent from inverter 711 as well as control signals CSA and CSB of H level, and generates test mode signal TM of H level.
In this manner, each of DRAMs 631-648 is shifted to the test mode when used alone, and is subjected to various operation tests.
In the RDIMM provided with the DRAMs, however, the voltage level of the externally supplied signal is converted to the voltage level for use in the RDIMM before being output to the DRAM, as already described. Therefore, in the semiconductor module such as an RDIMM, a signal (SVIH) formed of a high voltage level shifting the DRAM to the test mode cannot be applied to the DRAMs. Consequently, the semiconductor module suffers from such a problem that the DRAM in the module cannot be shifted to the test mode.
Accordingly, an object of the invention is to provide a semiconductor memory device, which can be shifted to a test mode in a module.
Another object of the invention is to provide a semiconductor module, in which a semiconductor memory device can be shifted to a test mode.
A semiconductor memory device according to the invention includes a power supply terminal for receiving a power supply voltage; a memory cell array including a plurality of memory cells; a peripheral circuit for inputting and outputting data to and from the plurality of memory cells; and a test mode circuit for operating, in an operation of shifting to a test mode, to detect a voltage level of a power supply voltage supplied from the power supply terminal in response to external input of a test mode shift signal, and generate a test mode signal for testing a special operation when the detected voltage level is different from the voltage level in a normal operation. The peripheral circuit performs input and output of data used for testing the special operation of each of the plurality of memory cells in response to the test mode signal.
For shifting the semiconductor memory device of this invention to the test mode, the device is supplied with the power supply voltage having a voltage level different from the voltage level used in the normal operation. When the power supply voltage thus supplied is detected, the semiconductor memory device can be shifted to the test mode. According to the invention, therefore, the semiconductor memory device can be shifted to the test mode by receiving the power supply voltage with the voltage level different from the voltage level in the normal operation. Consequently, it is possible to shift the semiconductor memory device to the test mode in the semiconductor module provided with the buffer circuit, which converts the externally supplied signal to the signal formed of the voltage level used in the module.
Preferably, the test mode shift signal is formed of first and second test mode shift signals, the power supply voltage is formed of first and second power supply voltages, the test mode circuit detects the voltage level of the first power supply voltage in response to the first test mode shift signal, detects the voltage level of the second power supply voltage in response to the second test mode shift signal, and generates the test mode signal when the detected voltage level of the second power supply voltage is different from the detected voltage level of the first power supply voltage.
For shifting to the test mode, the two power supply voltages with different voltage levels are supplied to the semiconductor memory device. When the voltage level of one of the supplied power supply voltages is different from the voltage level of the other power supply voltage, the semiconductor memory device enters the test mode. According to the invention, therefore, it is possible to shift the semiconductor memory device to the test mode by supplying the two power supply voltages of different voltage levels. As a result, the semiconductor memory device can be shifted to the test mode in the semiconductor module provided with the buffer circuit, which converts the externally supplied signal to the signal formed of the voltage level used in the module, and applies it to the semiconductor memory device.
Preferably, the test mode circuit generates the test mode signal when the detected voltage level of the second power supply voltage is higher than the detected voltage level of the first power supply voltage.
For shifting to the test mode, the two power supply voltages of different voltage levels are supplied to the semiconductor memory device. When the voltage level of one of the supplied power supply voltages is higher than the voltage level of the other power supply voltage, the semiconductor memory device is shifted to the test mode. In this invention, therefore, the semiconductor memory device can be shifted to the test mode by supplying successively the power supply voltage having a predetermined voltage level and the power supply voltage having a voltage level higher than the predetermined voltage level. As a result, the semiconductor memory device can be shifted to the test mode in the semiconductor module provided with the buffer circuit, which converts an externally supplied signal to the signal formed of the voltage level used in the module, and applies it to the semiconductor memory device.
Preferably, the first power supply voltage is a power supply voltage supplied in the normal operation.
For shifting to the test mode, the first power supply voltage used in the normal operation mode and the second power supply voltage higher in voltage level than the power supply voltage in the normal operation are supplied to the semiconductor memory device. When the first and second power supply voltages are detected, the semiconductor memory device enters the test mode. According to this embodiment, therefore, the semiconductor memory device can enter the test mode without a malfunction.
Preferably, the test mode circuit includes a level detecting circuit for detecting the voltage level of the first or second power supply voltage, and outputting a first level signal indicative of the detected voltage level of the first power supply voltage and a second level signal indicative of the detected voltage level of the second power supply voltage; and a signal generating circuit for generating a first detection signal based on the first level signal and the first test mode shift signal, generating, based on the second level signal and the second test mode shift signal, a second detection signal indicating that the detected voltage level of the second power supply voltage is higher than the detected voltage level of the first power supply voltage, and outputting the generated first and second detection signals as the test mode signals.
The two level signals indicating the voltage levels of the two power supply voltages are generated, and the detection signal for the power supply voltage with the lower voltage level and the detection signal for the power supply voltage with the higher voltage level are generated based on the two level signals and the two test mode shift signals. Thereby, the semiconductor memory device is shifted to the test mode. According to the invention, therefore, the semiconductor memory device can accurately enter the test mode based on the voltage levels of the detected two power supply voltages.
Preferably, the level detecting circuit is formed of a voltage dividing circuit for dividing the first or second power supply voltage to generate a first or second divided voltage, and a comparing circuit for comparing the voltage level of the first or second divided voltage with a reference voltage level to output the first or second level signal.
By comparing the divided voltage of the power supply voltage with the reference voltage, the voltage level of the power supply voltage is detected. According to the invention, therefore, the voltage levels of the two power supply voltages, which are different from each other, can be accurately detected. Consequently, the semiconductor memory device can accurately enter the test mode.
Preferably, the level detecting circuit is formed of a voltage dividing circuit for dividing the first or second power supply voltage to generate a first or second divided voltage, and a comparing circuit for comparing the voltage level of the first or second divided voltage with a first reference voltage level to output a first comparison result signal, comparing the voltage level of the first or second divided voltage with a second reference voltage level higher than the first reference voltage level to generate a second comparison result signal, and outputting the first or second level signal based on the generated first and second comparison result signals.
The two divided voltages with the different voltage levels produced by dividing the power supply voltages are compared with the two reference voltages with the different voltage levels, whereby the different voltage levels of the two power supply voltages are detected. According to the invention, therefore, it is possible to prevent erroneous shifting to the test mode due to variations in voltage levels during rising of the power supply voltage.
Preferably, the voltage dividing circuit is activated only in an operation of shifting to the test mode.
Only when the semiconductor memory device is to be shifted to the test mode, the power supply voltage is divided, and the voltage level of the power supply voltage is detected. According to the invention, therefore, the power consumption of the semiconductor memory device can be reduced.
Preferably, the test mode circuit further includes an activating circuit for selectively activating and deactivating the signal generating circuit in response to a type of a semiconductor module equipped with the semiconductor memory device.
The test mode circuit is activated and deactivated by the semiconductor module equipped with the semiconductor memory device. According to the invention, therefore, it is possible to select the circuit or unit for shifting the semiconductor memory device to the test mode in response to the type of the semiconductor module.
Preferably, the activating circuit is formed of a power supply node, an output node, a resistance element connected between the power supply node and the output node, and a fuse connected between the output node and the ground node.
By blowing or not blowing off the fuse, the signal generating circuit is activated or deactivated. According to the invention, therefore, the semiconductor module for mounting the semiconductor memory device therein can be determined after the production of the semiconductor memory device, and the semiconductor memory device can enter the test mode in the semiconductor module thus determined.
Preferably, the first power supply voltage is lower in voltage level than a standard power supply voltage supplied in the normal operation, and the second power supply voltage is higher in voltage level than the standard power supply voltage.
For shifting to the test mode, the two power supply voltages having the voltage levels different from the voltage level in the normal operation are supplied to the semiconductor memory device, and the semiconductor memory device enters the test mode when the two power supply voltages are detected. According to the invention, therefore, the semiconductor memory device can accurately enter the test mode.
Preferably, the test mode circuit generates the test mode signal when the detected voltage level of the second power supply voltage is lower than the detected voltage level of the first power supply voltage.
For shifting to the test mode, the two power supply voltages with different voltage levels are supplied to the semiconductor memory device, and the semiconductor memory device enters the test mode when the power supply voltages with the higher and lower voltage levels are successively detected. According to the invention, therefore, the semiconductor memory device, which is supplied with the power supply voltage with the high voltage level in the normal operation, can accurately enter the test mode.
Preferably, the second power supply voltage is a power supply voltage supplied in the normal operation.
For shifting to the test mode, the semiconductor memory device is successively supplied with the power supply voltage having the voltage level higher than the voltage level in the normal operation and the power supply voltage having the voltage level in the normal operation. When the two power supply voltages are detected, the semiconductor memory device enters the test mode. According to the invention, therefore, the semiconductor memory device can be shifted to the test mode by supplying the power supply voltage having the voltage level higher than the voltage level in the normal operation. Consequently, the semiconductor memory device can accurately enter the test mode.
Preferably, the power supply terminal is formed of a first power supply terminal for receiving a first power supply voltage used in the normal operation, and a second power supply terminal for receiving a second power supply voltage. The test mode circuit generates the test mode signal when detecting in accordance with the input of the test mode shift signal that the voltage level of the second power supply voltage is higher than the voltage level of the first power supply voltage.
For shifting to the test mode, the first and second power supply voltages with the different voltage levels are simultaneously supplied to the semiconductor memory device. When the voltage level of the second power supply voltage is higher than the voltage level of the first power supply voltage, the semiconductor memory device enters the test mode. According to the invention, therefore, the semiconductor memory device can accurately enter the test mode by using the power supply voltages having the voltage levels different from the voltage level in the normal operation.
Preferably, the test mode circuit includes a comparing circuit for comparing a voltage level of a divided voltage produced by dividing the second power supply voltage with the voltage level of the first power supply voltage, and outputting a comparison result and a signal generating circuit for generating the test mode signal in response to the test mode shift signal when the comparison result indicates that the voltage level of the divided voltage is higher than the voltage level of the first power supply voltage.
For shifting to the test mode, the supplied power supply voltage is divided for detecting the voltage level of the supplied power supply voltage. When the detected voltage level is higher than the voltage level in the normal operation, the semiconductor memory device is shifted to the test mode. According to the invention, therefore, it is possible to detect accurately the voltage level of the power supply voltage supplied at the time of shifting to the test mode. As a result, the semiconductor memory device can be accurately shifted the test mode.
A semiconductor memory device according to the invention includes a power supply terminal for receiving a power supply voltage; a memory cell array including a plurality of memory cells; a peripheral circuit for inputting and outputting data to and from each of the plurality of memory cells; and a test mode circuit for operating, in an operation of shifting to a test mode, to produce a plurality of logic signals based on the power supply voltage, and to output the plurality of produced logic signals as test signals indicating contents of the test for the memory cell. The peripheral circuit performs input and output of data used for executing the test in response to a logical pattern of the plurality of logic signals.
In the semiconductor memory device according to the invention, the plurality of logic signals are produced based on the supplied power supply voltage when the device is to be shifted to the test mode. Tests of different contents are performed in response to the combination of the logical levels of the plurality of produced logic signals. According to the invention, therefore, various operation tests can be performed in the semiconductor memory device without particularly employing a circuit for indicating the test contents.
Preferably, the test mode circuit includes a level detecting circuit for dividing the power supply voltage to a plurality of divided voltages having different voltage levels, respectively, and comparing the plurality of divided voltages with a reference voltage level to generate a plurality of level signals indicating the voltage levels of the plurality of divided voltages; and a signal generating circuit for generating the plurality of logic signals based on an externally applied test mode shift signal and the plurality of level signals.
The plurality of divided voltages with different voltage levels are produced from the one power supply voltage, and the plurality of logic signals, which have the logical levels corresponding to the voltage levels of the plurality of divided voltages, are generated. According to the invention, therefore, tests of different contents can be performed by changing the voltage level of the power supply voltage supplied to the semiconductor memory device in an operation of shifting to the test mode.
Preferably, the level detecting circuit includes a voltage dividing circuit for dividing the power supply voltage to the plurality of divided voltages, and a comparing circuit for comparing the plurality of divided voltages with the reference voltage level to generate the plurality of level signals.
The plurality of divided voltages with the different voltage levels are produced from the one power supply voltage. The respective voltage levels of the plurality of divided voltages are compared with the reference voltage level, and the plurality of level signals indicating the respective voltage levels of the plurality of divided voltages are generated. According to the invention, therefore, the voltage levels of the plurality of divided voltages produced from the one power supply voltage can be accurately detected. As a result, the plurality of logic signals with the different logical levels can be accurately generated.
A semiconductor module according to the invention includes a PLL circuit for generating a clock signal formed of a predetermined frequency; a registered buffer circuit for converting an externally supplied input signal to an input signal formed of a voltage level for internal use, and outputting the converted input signal in synchronization with the clock signal; a power supply terminal for receiving a power supply voltage; and a plurality of semiconductor memory devices for receiving the input signal from the registered buffer circuit and operating in synchronization with the clock signal. Each of the plurality of semiconductor memory devices includes a memory cell array including a plurality of memory cells, a peripheral circuit inputting/outputting data to and from each of the plurality of memory cells, and a test mode circuit detects the voltage level of the power supply voltage supplied from the power supply terminal in response to input of a test mode shift signal from the registered buffer circuit, and generating a test mode signal for testing a special operation based on the test mode shift signal. The peripheral circuit performs input/output of data used for testing the special operation to and from each of the plurality of memory cells in response to the test mode signal.
For shifting the semiconductor memory device to the test mode in the semiconductor module according to the invention, the voltage level of the externally supplied power supply voltage is detected, and thereby the semiconductor memory device is shifted to the test mode. According to the invention, therefore, the semiconductor memory device can be shifted to the test mode in the module.
Preferably, the test mode circuit produces a plurality of logic signals having logical levels corresponding to the detected voltage level, and outputs the plurality of produced logic signals as test signals indicating contents of the test of the memory cells. The peripheral circuit performs input and output of data used for executing the test in response to a logical pattern of the plurality of logic signals.
When shifted to the test mode, the plurality of logic signals are produced based on the power supply voltage supplied to the device, and contents of the test are determined in response to the combination of the logical levels of the plurality of logic signals. According to the invention, therefore, various operation tests of the semiconductor memory device can be performed in the module without particularly employing a circuit for designating the test contents.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.